Toshiba’s 3D NAND Chip

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Toshiba today announced a new three dimensional (3D) memory cell structure the squeezes more into less by changing the way the various elements are stacked, in this case, 3D.

Existing 2D technologies stack two-dimensional memory array on top of another, repeating the same set of processes.

In contrast, the 3D increases memory cell density, is easier to fabricate, and does not produce much increase in chip area, as peripheral circuits are shared by several silicon pillars, the company explained.

NAND flash memory functions through batch processing of cells, in large numbers of elements connected in series. Toshiba’s new array increases density without increasing chip dimension, as the number of connected elements increases in direct proportion to stack height (32-layer stack realizes 10 times the integration of a standard chip formed with the same generation of technology)